• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device in which a defect caused by damage of an interlayer insulating film in a metal wiring process can be solved by further forming a buffer layer outside the metal wiring. Step; Forming a stress buffer layer to block physical and thermal stress by the O 2 plasma process on the side of the metal wiring; Forming a first IMD layer on the front surface and forming an insulating layer for planarization by SOG coating process on the front surface ; Forming a second IMD layer on the planarization insulating layer and performing an annealing process to relieve thermal stress.
    公开号:KR20020017310A
    申请号:KR1020000050533
    申请日:2000-08-29
    公开日:2002-03-07
    发明作者:임비오；이명신
    申请人:박종섭；주식회사 하이닉스반도체；
    IPC主号:
    专利说明:

    METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE
    [9] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for forming a metal wiring in a semiconductor device in which a defect caused by damage of an interlayer insulating film in a metal wiring process can be solved by further forming a buffer layer outside the metal wiring.
    [10] Hereinafter, a metal wire of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
    [11] 1 is a cross-sectional view of a structure of a metal wiring of a semiconductor device of the prior art, and FIGS. 2A and 2B are cross-sectional photographs illustrating pinholes in a metal wiring of a semiconductor device of the prior art.
    [12] The basic structure of the metal wiring of the semiconductor device of the prior art firstly comprises a metal wiring 2 used as the main wiring layer on the substrate 1 and an ARC for suppressing diffuse reflection of light during patterning of the metal wiring 2. Anti-Rectifier Coating (3), a first IMD (Inter Metal Dielectric) layer (4) formed on the entire surface, a planarization insulating layer (5) formed on the first IMD layer (4), And a second IMD layer 6 for protecting another metal wiring formed on the planarization insulating layer.
    [13] Such a metal wire of the prior art is a portion in which stress is intensively applied due to damage of the interlayer insulating layer at ㉮ and ㉯ of FIG. 1.
    [14] As shown in Figures 2a and 2b, 0.18㎛ Tech. The metal voids generated during the aluminum metal wiring process may cause various defects in the device.
    [15] This is because the oxynitride film used in the interlayer insulating film process of metal wiring, the curing of SOG (420 ° C. 30min) → the etch back of SOG → the physical arising in the process of forming the second IMD layer, Voids are known to cause voids due to thermal stress, SOG shrinkage during SOG curing, and have a lethal effect on stress weak aluminum.
    [16] Such a metal wiring formation method of the semiconductor element of the prior art has the following problem.
    [17] In the curing and etching process for forming the metal wires, the stress applied to the metal wires cannot be blocked, thereby causing a fatal effect on aluminum to generate voids.
    [18] Such voids result in a decrease in the cross-sectional area of the metal wiring, thereby increasing the resistance. This causes the device to fail and degrade the device's reliability.
    [19] The present invention is to solve the problem of the metal wiring of the semiconductor device of the prior art, a semiconductor that can solve the defect caused by damage of the interlayer insulating film in the metal wiring process by forming a buffer layer outside the metal wiring further It is an object of the present invention to provide a method for forming a metal wiring of an element.
    [1] 1 is a structural cross-sectional view of a metal wiring of a semiconductor device of the prior art
    [2] 2A and 2B are cross-sectional photographs showing pinholes in a metal wiring of a semiconductor device of the prior art;
    [3] 3A to 3C are cross-sectional views of a metal wiring of a semiconductor device according to the present invention.
    [4] -Explanation of symbols for the main parts of the drawing-
    [5] 31. Substrate 32. Metal Wiring
    [6] 33. ARC layer 34. First IMD layer
    [7] 35. Stress buffer layer 36. Insulation layer for planarization
    [8] 37. Second IMD Layer
    [20] Method for forming a metal wiring of the semiconductor device according to the present invention for achieving the above object; Forming a metal wiring on a substrate; A stress buffer layer for blocking physical and thermal stress by the O 2 plasma process on the side of the metal wiring Forming a first IMD layer on the front surface and forming a planarization insulating layer on the front surface by a SOG coating process; forming a second IMD layer on the planarization insulating layer and anneal process to reduce thermal stress Characterized in that it comprises a step of proceeding.
    [21] Hereinafter, a metal wire forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
    [22] 3A to 3C are cross-sectional views of a metal wiring of a semiconductor device according to the present invention.
    [23] Metal wiring of the semiconductor device according to the present invention is a metal wiring 32 used as the main wiring layer on the substrate 31, and ARC (Anti-Rectifier Coating) for suppressing diffuse reflection of light at the time of patterning the metal wiring 32 Layer 33, a stress buffer layer 35 formed on the side surface of the metal wiring 32 to block stress applied to the wiring itself, and a first IMD (Inter Metal Dielectric) layer 34 formed on the entire surface thereof. And a planarization insulating layer 36 formed on the first IMD layer 34 and a second IMD layer 37 for protecting another metal wiring formed on the planarizing insulating layer. .
    [24] Such a manufacturing process of the metal wiring according to the present invention is as follows.
    [25] First, as shown in FIG. 3A, a material layer for forming metal wiring such as aluminum is formed on the substrate 31.
    [26] Subsequently, the metal wire 32 is formed by performing a mask forming process and an etching process.
    [27] After the cleaning process using the solvent, the Al 2 O 3 stress buffer layer 35 is formed on the side surface of the metal wiring 32 in the O 2 plasma process as shown in FIG. 3B.
    [28] Here, the plasma density is set to 50 W to 2 KW.
    [29] Subsequently, after the O 2 plasma treatment, oxynitride is deposited to form a first IMD layer 34.
    [30] Here, the first IMD layer 34 is deposited under conditions that alleviate the tensile stress generated during the subsequent SOG coating and curing process.
    [31] This is to relieve this stress to some extent because the side stress caused by SOG contraction is so large.
    [32] 3C, the planarization insulating layer 36 is formed on the entire surface by the SOG coating process.
    [33] Here, the densify temperature and time are proceeded to 400 ° C. and 30 Min in consideration of thermal stress generated by curing.
    [34] Lowering the temperature no longer completely densify the SOG, which may cause via voids in subsequent processes, so 400 to 410 ° C is most appropriate.
    [35] The planarization insulating layer 36 is planarized to form a second IMD layer 37.
    [36] Here, H 2 + N 2 annealing is performed at a temperature of 420 ° C. for 100 minutes to alleviate thermal stress due to high temperature.
    [37] The present invention improves the reliability of wiring by forming a stress buffer layer between the side of the metal wiring and the first IMD layer in order to minimize the force applied to the metal wiring by the thermal and physical stress generated when SOG is used as the interlayer insulating film. Can be.
    [38] Such a metal wiring formation method of a semiconductor device according to the present invention has the following effects.
    [39] A stress buffer layer may be formed between the side surfaces of the metal wiring and the first IMD layer to suppress wiring defects due to stress caused by the IMD layer and shrinkage of the SOG layer generated during the curing process.
    [40] This reduces T-bit or lcc fail, resulting in higher device yield and higher device reliability.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] Forming a metal wiring on the substrate;
    Forming a stress buffer layer on a side of the metal wire to block physical and thermal stresses by an O 2 plasma process;
    Forming a first IMD layer on the front surface and a planarization insulating layer on the front surface by a SOG coating process;
    And forming a second IMD layer on the planarization insulating layer and performing an annealing process to alleviate thermal stress.
    [2" claim-type="Currently amended] 2. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the metal wiring is formed of aluminum and the stress buffer layer is formed of an Al 2 O 3 layer.
    [3" claim-type="Currently amended] The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the annealing process is performed for 100 minutes at a temperature of 420 ° C in an H 2 + N 2 atmosphere.
    [4" claim-type="Currently amended] The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the O 2 plasma process is performed after the metal wiring is formed and the cleaning process is performed, and the plasma density is set to 50 W to 2 KW.
    [5" claim-type="Currently amended] 2. The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the first and second IMD layers are formed of oxynitride.
    [6" claim-type="Currently amended] The method for forming a metal wiring of a semiconductor device according to claim 1, wherein the curing temperature and time for forming the SOG layer are advanced at 400 to 410 캜 for 30 minutes.
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    同族专利:
    公开号 | 公开日
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2000-08-29|Application filed by 박종섭, 주식회사 하이닉스반도체
    2000-08-29|Priority to KR1020000050533A
    2002-03-07|Publication of KR20020017310A
    优先权:
    申请号 | 申请日 | 专利标题
    KR1020000050533A|KR20020017310A|2000-08-29|2000-08-29|Method for forming metal line of semiconductor device|
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